1. Field of the Invention
The invention relates to a method for producing a plurality of integrated semiconductor components.
2. Description of the Related Art
Integrated semiconductor components are generally not produced individually, but rather are manufactured as an array on a carrier, e.g. on a silicon wafer. Know methods for producing integrated semiconductor components require many steps to produce components suitable for a particular application.
One such application is in the field of power electronics circuits, which require so-called snubber networks, or “snubbers”. Snubbers dissipate parasitic energies in the relevant circuit or withdraw them from the circuit and feed them back later. Snubbers, generally consist of simple interconnections of resistances, capacitances and inductances. In a snubber component of this type, e.g., an RC element, the parasitic energy is dissipated, e.g., in the form of heat.
German Published Patent Application DE 10 2006 017 487 A1 discloses producing snubbers in an integrated design as an integrated semiconductor component. In accordance with the publication “Berberich, S. E.; Bauer, A. J.; Ryssel, H., High Voltage 3D-Capacitor, 12th European Conference on Power Electronics and Applications 2007 Proceedings EPE '07, 2-5 Sep. 2007, Aalborg, Denmark”, it is known to fabricate integrated snubber components as 3D snubbers in a production process which constitutes a derivative of a standardized CMOS silicon technology. The electrical properties of the components are controlled, inter alia, by the intensity of the doping of the semiconductor materials and the area or size of the components.
In other words, photolithography steps are used for scaling the component base area or defining the chip area and for patterning the metallization.
The technology described results in great process engineering complexity. Furthermore, the complexity for scaling the components, i.e., with regard to their chip size, capacitance value and resistance value of the snubber components, is high. For changing the resistance, in this case, e.g., the area of the respective chip or the doping of the wafer is changed. For changing the capacitance of a component, the component area is altered, e.g. an area of approximately 15 μm2 is required for producing a 15 nF capacitor having a dielectric strength of greater than 200 V, and approximately 20 μm2 for a 20 nF capacitor.